Copper Road

EssayMay 29, 2026

The boxes aren't the bottleneck

Every forecast for the AI buildout is written in GPUs. It's the wrong unit.

15 bottlenecks — sorted by tightness

PowerMay 28, 2026

Gas turbines

The fastest dispatchable power for AI data centers — and only three makers globally. Backlogs stretch ~5 years, with delivery slots already selling into 2030.

Large power transformers

The heavy iron that steps power up and down for the grid. Lead times have blown out to ~5 years — under 10% of data-center cost, but effectively 100% of the bottleneck.

Compute & siliconMay 28, 2026

Leading-edge foundry (2nm / N2)

The single source of the world's most advanced transistors. TSMC's N2 is sold out through 2026 with orders pushing into 2028 — and there is no real second supplier at the leading edge.

Server DRAM supply

HBM is cannibalizing the DRAM wafer pool: makers are pouring capacity into high-margin AI memory, dragging conventional server DRAM into a sold-out supercycle with the steepest price increases in over a decade.

Silicon & packagingMay 28, 2026

CoWoS advanced packaging

The gate on every advanced AI accelerator shipped — if a chip needs HBM, it needs CoWoS, and capacity is effectively sold out.

Grid power & interconnection

Power is now the binding constraint on the AI buildout — ahead of chips. The bottleneck has migrated from the server rack to the substation, with interconnection queues and heavy electrical gear taking years.

Compute & siliconMay 29, 2026

EUV lithography

Every sub-7nm logic chip and advanced DRAM is patterned on an EUV scanner, and ASML is the only company on earth that builds them — a textbook monopoly whose finite output rate is the hard ceiling on leading-edge capacity worldwide.

Compute & siliconMay 29, 2026

Custom silicon (hyperscaler ASICs)

Hyperscalers are designing their way around Nvidia with bespoke accelerators — but only two firms can co-design them at scale, and they all funnel through the same TSMC nodes and CoWoS slots.

HBM (high-bandwidth memory)

The memory that makes an accelerator usable — stacked DRAM bonded beside the GPU. Bandwidth, not compute, is the binding constraint, and supply is sold out across all three makers through 2026.

Optical & interconnectMay 28, 2026

Optical transceivers (800G / 1.6T)

The interconnect that wires GPU clusters together — roughly six per GPU. 800G is running well below demand, and Nvidia spent $4B locking up the laser supply.

Compute & siliconMay 29, 2026

Silicon interposers

The passive silicon slab that wires HBM to logic inside CoWoS is reticle-limited and eats TSMC wafer capacity — so as AI packages balloon past reticle size, usable interposers per wafer collapse and packaging can't scale faster.

Compute & siliconMay 29, 2026

ABF substrates

AI accelerators need far larger, higher-layer-count substrates than any prior chip, and a five-firm oligopoly is heading back into shortage on what suppliers call a three-year super-cycle.

Compute & siliconMay 29, 2026

Wafer fab equipment

Every new fab is built from tools made by a handful of segment monopolists, and the AI cycle (leading-edge logic + DRAM/HBM + advanced packaging) is driving a higher-intensity WFE wave with long lead times that gates how fast capacity can come online.

Cooling & thermalMay 28, 2026

Liquid cooling (direct-to-chip)

Above ~30–50 kW per rack, air cooling fails — so next-gen GPUs make liquid cooling mandatory, not optional. This is a fast transition more than a hard shortage.

Compute & siliconMay 29, 2026

Silicon wafers (300mm)

A two-speed market: AI-grade ultra-flat 300mm for 2/3nm is tightening even as legacy 200mm softens — so headline 'wafer demand' masks a real squeeze on exactly the wafers AI needs, sitting on a five-firm oligopoly with multi-quarter qualification moats.